In the optoelectronics industry, silicon photonics and photonics modules are key enabling technologies and platforms for potentially revolutionary advances in the optical communication systems, data communications, security, and sensing. Silicon photonics has the potential to realize small, highly integrated, photonics sub-systems that take advantage of integrated circuit (IC) fabrication technology and scalability to achieve the full potential of these platforms. Further, multi-chip integration of silicon photonics allows for the bridging of different functional technologies, such as micro-electro-mechanical systems (MEMS), III-V materials, non-complimentary metal-oxide semiconductor (CMOS) application-specific integrated circuits (ASIC), etc.
A typical silicon photonics package using multi-chip integration may include a photonic integrated circuit (PIC) chip attached with optical fibers and a trans-impedance amplifier (TIA) chip that are interconnected with conducting wires (e.g., wire bonds). Ideally, a constant bandwidth is desirable in transmission/reception of signals in the silicon photonic package. Additionally, it is also desirable to increase and maximize the overall bandwidth of the silicon photonics package.
One possible approach to achieving increased and stabilized bandwidth value is to predetermine an inductance value in the conducting wires between the PIC chip and the TIA chip, which is dependent on the resulting wire length used for wire bonding. However, due to demands for reduced physical sizes and increased density of elements in semiconductor packaging, as well as process variations in the packaging process, the resulting interconnecting wires used in the silicon photonic package may have varying lengths and loop height leading to variable bandwidth values, higher parasitic inductance and poorer device performance. Furthermore, the dimensional variability of interconnecting wires due to process variations may limit the potential to increase the overall bandwidth of the package.
Therefore, it is desirable to achieve an optimized semiconductor packaging of silicon photonics whereby the bandwidth is stable and maximised, and yet able to deliver smaller packaging footprints with improved device performance.